DFT Engineer

DFT Engineer Overview

An exciting opportunity has arisen for a DFT Engineer to join a dynamic ASIC team focused on the development of next-generation silicon in Cambridge. This innovative technology company is expanding its team following the successful delivery of multiple production ASICs, and they are looking for a skilled professional to contribute to their ongoing projects.

As a DFT Engineer, you will be integral to the development of robust Design-for-Test solutions for future ASICs, ensuring that high-quality silicon is produced for volume manufacturing while balancing test coverage, implementation complexity, and time-to-market. You will work collaboratively throughout the entire silicon development lifecycle, from architecture and specification through to design, verification, implementation, manufacturing testing, and production.

Key Responsibilities:

• Define DFT strategies at chip, subsystem, and IP levels.
• Implement structural and functional DFT methodologies across complex ASIC designs.
• Insert and integrate scan, MBIST, EDT, SSN, and IJTAG-based test infrastructure.
• Verify DFT implementation and debug related issues throughout the design cycle.
• Support implementation and sign-off, including timing constraints, timing closure, power analysis, and formal equivalence checking.
• Work closely with Physical Design and Verification teams to ensure successful integration.
• Support ATPG generation, silicon bring-up, and manufacturing test.
• Mentor and support other engineers within the team.

Qualifications:

• Experience working within modern ASIC or SoC development flows.
• Strong experience with Siemens Tessent DFT tools.
• Good understanding of complex DFT challenges, including clocking, reset architecture, and IP integration.
• Experience with ATPG, MBIST, scan architecture, DFT verification, and simulation debug.
• Familiarity with UPF and low-power verification concepts.
• Good Tcl scripting skills; Python knowledge is also beneficial.
• A collaborative approach with excellent troubleshooting and debugging skills.

Desirable Experience:

• Knowledge of advanced silicon technologies and manufacturing fault models.
• Familiarity with IJTAG / IEEE 1687 and related test access standards.
• Experience supporting vector translation and production bring-up on ATE platforms.
• Previous experience mentoring or coaching other engineers.

If you are passionate about solving technically challenging problems and enjoy collaborating with experienced engineers, this role offers a chance to take ownership of high-quality DFT implementation from architecture through to production. Interested candidates are encouraged to reach out for more details.

Degree Requirement: Not Specified

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