Lead RTL Designer PPA Experience

Lead RTL Designer PPA Experience Overview

Fractile is seeking a highly skilled Lead RTL Designer with expertise in PPA (Power, Performance, Area) optimization and microarchitecture design for datapaths. Founded in 2022, Fractile focuses on revolutionizing hardware to accelerate AI inference speeds, enabling large models to operate efficiently at high throughput. The company aims to address the technical and economic challenges limiting inference speed, which are critical for advancements in fields like drug discovery, software engineering, and materials science.

About the Role

The successful candidate will take ownership of designing and optimizing datapath components, including pipelining, retiming, and balancing parallelism against area and power constraints to meet stringent PPA targets. You will lead efforts to identify bottlenecks in the design, propose RTL modifications, and validate their impact through rigorous testing. Your work will involve developing timing-aware RTL code, iterating through synthesis and static timing analysis, and applying low-power techniques to enhance efficiency. Collaboration with physical design engineers will be essential to ensure PPA goals are achieved effectively. Additionally, you will utilize formal verification tools to maintain RTL correctness and work with synthesis tools like Synopsys Design Compiler, Fusion Compiler, and Cadence Genus, as well as IP libraries such as DesignWare.

Key Responsibilities

• Design and optimize datapath microarchitecture components, focusing on pipelining, retiming, and parallelism-area trade-offs.
• Drive the entire PPA closure process by pinpointing performance bottlenecks, implementing RTL changes, and validating their effectiveness.
• Create RTL designs that are aware of timing constraints, refining them through synthesis and static timing analysis feedback.
• Implement low-power design techniques to improve chip efficiency.
• Work closely with physical design teams to facilitate PPA closure, sharing insights and strategies.
• Use formal verification and equivalence checking to ensure RTL correctness throughout the design cycle.
• Leverage and contribute to IP libraries and generator tools to streamline datapath design.
• Bring experience with AI/ML accelerator datapaths, such as systolic arrays and tensor engines, to enhance high-performance compute capabilities.

Candidate Requirements

• Strong background in microarchitecture design for datapaths, with expertise in pipelining, retiming, and balancing parallelism against area and power.
• Proven success in achieving PPA improvements from design to silicon, including bottleneck identification and RTL validation.
• Deep understanding of fixed-point, floating-point, and quantized arithmetic design principles.
• Ability to analyze PPA trade-offs and translate targets into concrete RTL and microarchitectural decisions.
• Experience with low-power design techniques.
• Proficiency in writing timing-aware RTL code and iterating based on synthesis and static timing analysis results.
• Familiarity with synthesis tools such as Synopsys Design Compiler, Fusion Compiler, and Cadence Genus, along with IP libraries like DesignWare.
• Demonstrated capability to deliver measurable PPA improvements on production chips or datapaths.
• Experience with formal verification and equivalence checking to ensure RTL correctness.
• Physical design awareness to collaborate effectively with physical design teams on PPA closure.

What We Offer

• A competitive salary reflecting your experience and the specialized nature of this role.
• Meaningful equity participation, sharing in the company’s growth and success.
• Comprehensive benefits including private medical, dental, and vision insurance, along with a contributory pension scheme.
• 25 days of holiday plus bank holidays, and access to life and critical illness insurance.
• A dynamic, inclusive office environment that values diverse perspectives and innovative thinking.
• The opportunity to join a rapidly growing company backed by significant investment, with a mission to accelerate global progress through advanced chip design.

Additional Information

The company’s work involves technologies subject to export control laws in the UK, US, and other jurisdictions. Some roles may require additional eligibility checks to ensure compliance, and the company commits to transparency throughout the hiring process.

Degree Requirement: Not Specified

Visa Sponsorship May be