Staff Verification Engineer

Staff Verification Engineer Overview

An exciting opportunity has arisen for a Staff Verification Engineer to join a pioneering hardware team in Cambridge, specializing in quantum computing and next-generation systems design. This role offers a competitive salary between £90,000 and £115,000, depending on experience, along with bonus potential and a comprehensive benefits package.

The successful candidate will be responsible for leading the verification strategy and execution across block, subsystem, and multi-FPGA designs. You will develop scalable, high-performance UVM environments to tackle complex architectures and drive verification with a strong focus on coverage, risk reduction, and system-level behavior. Collaboration will be key, as you will work closely with the Lead Verification Engineer and cross-functional hardware teams to debug challenging issues that span RTL, simulation, and hardware platforms.

To be considered for this role, you should possess strong hands-on expertise in SystemVerilog and UVM, along with proven debugging skills across RTL, simulation, and hardware. Experience in owning verification planning and strategy in commercial environments is essential, as is the ability to operate effectively in fast-moving environments with evolving requirements. Familiarity with software/programming languages such as C, C++, or Python is advantageous, and formal verification experience would be a plus.

This position provides a unique chance to work on groundbreaking technology within a team where your ideas and technical depth will significantly influence future developments. Visa sponsorship is available for engineers who are already based in the UK. For further details, please reach out to Rachel Mason at IC Resources.

Degree Requirement: Not Specified

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